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NCP1560 Full Featured Voltage Mode PWM Controller
The NCP1560 PWM controller contains all the features and flexibility needed to implement voltage- mode control in high performance single ended DC/DC converters. This device cost effectively reduces system part count with the inclusion of a high voltage start-up regulator that operates over a wide input range of 21.5 V to 150 V. The NCP1560 provides two control outputs, OUT1 which controls the main PWM switch and OUT2 with adjustable over-lap delay, which can control a synchronous rectifier switch or an active clamp/reset switch. Other distinctive features include: two mode over current protection, line under/over voltage lockout, fast line feedforward, soft start and a maximum duty cycle limit.
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16 SO-16 D SUFFIX CASE 751B 1 1 NCP1560 = Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week NCP1560 AWLYWW
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Minimum Operating Voltage of 21.5 V Internal High Voltage Start-up Regulator Dual Control Outputs with Adjustable Overlap Delay Single Resistor Oscillator Frequency Setting Fast Line Feedforward Line Under/Over Voltage Lockout Dual Mode Over Current Protection Programmable Maximum Duty Cycle Control Maximum Duty Cycle Proportional to Line Voltage Programmable Soft Start Precision 5.0 V Reference Telecommunication Power Converters Industrial Power Converters High Voltage Power Modules +42 V Automotive Systems Control Driven Synchronous Rectifier Power Converters
ORDERING INFORMATION
Device NCP1560HDR2 Package SO-16 Shipping 2500/Tape & Reel
Typical Applications
(c) Semiconductor Components Industries, LLC, 2003
1
January, 2003 - Rev. 5
Publication Order Number NCP1560/D
NCP1560
Vin
High Voltage Start-up Regulator 5.0 V Reference
VAUX
VREF
UV/OV CS
UV Fault Detection
Modulator
Delay Logic
Output Drivers
OUT1 OUT2
CSKIP RT Oscillator FF
tD
VEA SS GND
DCMAX
Figure 1. Simplified Block Diagram
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NCP1560
1 Vin 13.8 mA 16 VAUX CAUX 14 GND Disable_VREF Vin + 1.49 V 2 UV/OV + 3.6 V VREF Disable CSKIP 6 CCSKIP One Shot Pulse (600 ns) 5 CS + + 0.6 V + 0.5 V VREF CURRENT MIRROR 9 SS CSS 7 RT RT + 1.3 V* * Trimmed during manufacturing to obtain 1.3 V with RT = 101 kW Disable_ss I1 STOP 10 pF + 2V + ++ 2V 2V Clock V I+ 125 kW 4 FF IFF 5.3 kW 6.7 kW + V + 10 pF CFF One Shot Pulse FF Ramp (Adjustable) + VDC(inv) 27 kW 40 kW 32 kW 8 DCMAX RP VREF RMDP Oscillator Ramp I1 2 2V Max DC Comparator 2 kW 20 kW Soft Start - + Comparator +PWM Comparator 10 VEA 11 mA + + + 2V S Clock Q Delay Logic VAUX DIS 13 OUT2 VAUX + STOP + + 11 V/7 V S Q Monotonic Start Latch (Reset Dominant) R Disable_ss 12 tD DIS 15 Output Latch (Reset Dominant) R Disable_VREF One Shot Pulse (250 ns) 5.0 V Reference DIS VREF 11 Disable VAUX
RD
OUT1
+
Vin RFF
Figure 2. NCP1560 Functional Block Diagram http://onsemi.com
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NCP1560
PIN DESCRIPTION
Pin 1 Name Vin Application Information This pin is connected to the bulk DC input voltage supply. A constant current source supplies current from this pin to the capacitor connected on the VAUX pin. The charge current is typically 13.8 mA. Input voltage range is 21.5 V to 150 V. Input supply voltage is scaled down and sampled by means of a resistor divider. The supply voltage must be scaled down between 1.52 V and 3.61 V within the specified input voltage range. Not Connected. An external resistor between Vin and this pin adjusts the amplitude of the FF Ramp in proportion to Vin. By varying the feedforward ramp amplitude in proportion to the input voltage, changes in loop bandwidth are eliminated. Over current sense input. If the CS voltage exceeds 0.48 V or 0.57 V, the converter enters the Cycle by Cycle or Cycle Skip current limit mode, respectively. The capacitor connected between this pin and ground sets the Cycle Skip period. A soft start sequence follows at the conclusion of the fault period. A single external resistor between this pin and GND sets the oscillator fixed frequency. An external resistor between this pin and GND sets the voltage on the Max DC Comparator inverting input. The duty cycle is limited by comparing the voltage on the Max DC Comparator inverting input to the Feedforward Ramp. An internal 6.2 mA current source charges the external capacitor connected to this pin. The duty cycle is limited during start-up by comparing the voltage on this pin to the Oscillator Ramp. The error signal from an external error amplifier is fed into this input and compared to the Feedforward Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM Comparator inverting input. Precision 5.0 V reference output. Maximum output current is 6 mA. An external resistor between VREF and this pin sets the overlap delay between OUT1 and OUT2 transitions. Output of the PWM controller with leading and trailing edge overlap delay. OUT2 can be used to drive a synchronous rectifier topology, an active clamp/reset switch, or both. Control circuit ground. Main output of the PWM controller. Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An internal current supplies current from Vin to this pin. Once the voltage on VAUX reaches 11 V, the current source turns OFF. It turns ON again once VAUX falls to 7 V. During normal operation, power is supplied to the IC via this pin, by means of an auxiliary winding.
2 3 4
UV/OV NC FF
5 6 7 8
CS CSKIP RT DCMAX
9 10
SS VEA
11 12 13 14 15 16
VREF tD OUT2 GND OUT1 VAUX
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NCP1560
MAXIMUM RATINGS (Note 1)
Rating Input Line Voltage Auxiliary Supply Voltage Auxiliary Supply Input Current OUT1 and OUT2 Voltage OUT1 and OUT2 Output Current 5.0 V Reference Voltage 5.0 V Reference Output Current All Other Inputs/Outputs Voltage All Other Inputs/Outputs Current Operating Junction Temperature Storage Temperature Range Power Dissipation at TA = 25C Thermal Resistance, Junction to Ambient Symbol Vin VAUX IAUX VOUT IOUT VREF IREF VIO IIO TJ Tstg PD RqJA Value -0.3 to 150 -0.3 to 16 35 -0.3 to (VAUX + 0.3 V) 10 -0.3 to 6.0 6.0 -0.3 to VREF 10 -40 to 125 -55 to 150 0.77 130 Unit V V mA V mA V mA V mA C C W C/W
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. A. This device series contains ESD protection and exceeds the following tests: Pin 1 is the HV start-up of the device and is rated to the max rating of the part, or 150 V. Machine Model Method 150 V. Pins 2-16: Human Body Model 4000 V per MIL-STD-883, Method 3015. Machine Model Method 200 V.
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NCP1560
ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 kW, CCSKIP = 6800 pF, RD = 60.4 kW, RFF = 432 kW, for typical values TJ = 25C, for min/max values, TJ = -40C to 125C, unless otherwise noted)
Characteristic START-UP CONTROL AND VAUX REGULATOR VAUX Regulation Start-up Threshold/VAUX Regulation Peak (VAUX increasing) Minimum Operating VAUX Valley Voltage After Turn-On Hysteresis Minimum Start-up Voltage (Pin 1) ISTART = 1.0 mA, VAUX = VAUX(on) - 0.2 V Start-up Circuit Output Current VAUX = 0 V TJ = 25C TJ = -40C to 125C VAUX = VAUX(on) - 0.2 V TJ = 25C TJ = -40C to 125C Start-up Circuit Off-State Leakage Current (Vin = 150 V) TJ = 25C TJ = -40C to 125C Start-up Circuit Breakdown Voltage (Note 2) ISTART(off) = 50 mA, TJ = 25C Auxiliary Supply Current After VAUX Turn-On Outputs Disabled VEA = 0 V VUV/OV = 0.7 V Outputs Enabled LINE UNDER/OVERVOLTAGE DETECTOR Undervoltage Threshold (Vin Increasing) Undervoltage Hysteresis Overvoltage Threshold (Vin Increasing) Overvoltage Hysteresis Undervoltage Propagation Delay to Output Overvoltage Propagation Delay to Output CURRENT LIMIT Cycle by Cycle Threshold Voltage Propagation Delay to Output (VEA = 2.0 V) VCS = ILIM1 to 2.0 V, measured when VOUT reaches 0.5 VOH Cycle Skip Threshold Voltage Cycle Skip Charge Current (VCSKIP = 0 V) 2. Guaranteed by design only. ILIM1 tILIM ILIM2 ICSKIP 0.44 0.54 8.0 0.48 90 0.57 12.3 0.52 150 0.62 15 V ns V mA VUV VUV(H) VOV VOV(H) tUV tOV 1.40 0.080 3.47 1.52 0.098 3.61 0.145 250 160 1.64 0.120 3.75 V V V V ns ns V VAUX(on) VAUX(off) VH VSTART(min) ISTART 13 10 10 8 ISTART(off) V(BR)DS 150 23 50 100 V mA IAUX1 IAUX2 IAUX3 2.7 1.3 4.6 5.0 2.5 6.5 17.5 13.8 21 25 17 19 mA 19.3 21.5 mA 10.5 6.6 11.0 7.0 4.0 11.5 7.4 V Symbol Min Typ Max Unit
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NCP1560
ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 kW, CCSKIP = 6800 pF, RD = 60.4 kW, RFF = 432 kW, for typical values TJ = 25C, for min/max values, TJ = -40C to 125C, unless otherwise noted)
Characteristic OSCILLATOR Frequency (RT = 101 kW, Vin = 36 V) TJ = 25C TJ = -40C to 125C Frequency (RT = 59 kW, Vin = 36 V, VEA = 1 V) TJ = 25C TJ = -40C to 125C MAXIMUM DUTY CYCLE COMPARATOR Maximum Duty Cycle (Vin = 36 V, VEA = 3 V, TJ = 25C) RP = 0 W, RMDP = open RP = open, RMDP = open Open Circuit Voltage SOFT START Charge Current (VSS = 1.0 V) Discharge Current (VSS = 5.0 V, VUV/OV = 3.7 V) PWM COMPARATOR Input Resistance (V1 = 1.25 V, V2 = 1.50 V) RIN(VEA) = (V2 - V1)/(I2 - I1) Lower Input Threshold Delay to Output (from VOH to 0.5 VOH) 5.0 V REFERENCE Output Voltage (IREF = 0 mA) Load Regulation (IREF = 0 to 6 mA) Line Regulation (VAUX = 7.5 to 16 V) CONTROL OUTPUTS Output Voltage (IOUT = 0 mA) Low State High State Overlap Delay (Vin = 36 V) RD = 1 MW Leading Trailing RD = 60 kW Leading Trailing Drive Resistance (Vin = 15 V) Sink (VEA = 0 V, VOUT = 2 V) Source (VEA = 3 V, VOUT = 10 V) Rise Time (CL = 100 pF, 10% to 90% of VOH) Fall Time (CL = 100 pF, 90% to 10% of VOH) V VOL VOH tD 50 32 RSNK RSRC ton toff 20 50 200 170 90 72 40 90 30 12 130 130 W 80 170 ns ns 0.25 11.8 ns VREF VREF(Load) VREF(Line) 4.9 5.0 10 50 5.1 50 100 V mV mV RIN(VEA) VEA(L) tPWM 8.0 0.3 22 0.7 200 60 0.9 kW V ns ISS(C) ISS(D) 5.0 20 6.2 52.5 7.4 mA mA DCMAX 57 75 VDCMAX 0.40 62 80 0.47 66 85 0.60 V % fOSC1 285 280 fOSC2 456 444 480 504 516 300 315 320 kHz kHz Symbol Min Typ Max Unit
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NCP1560 Typical Characteristics
VAUX, AUXILIARY SUPPLY VOLTAGE (V)
12 ISTART, START-UP CIRCUIT OUTPUT CURRENT (mA) 11 10 9 8 7 6 5 -50 -25 0 25 50 MINIMUM OPERATING THRESHOLD 75 100 125 150 START-UP THRESHOLD
20 19 18 17 16 15 14 13 12 11 10 -50 VAUX = VAUX(on) - 0.2 V VAUX = 0 V Vin = 48 V
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 3. Auxiliary Supply Voltage Thresholds versus Junction Temperature
ISTART, START-UP CIRCUIT OUTPUT CURRENT (mA) ISTART, START-UP CIRCUIT OUTPUT CURRENT (mA) 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 0 2 4 6 8 10 12 VAUX, AUXILIARY SUPPLY VOLTAGE (V) Vin = 48 V 20
Figure 4. Start-up Circuit Output Current versus Junction Temperature
16
TJ = -40C
12
TJ = 25C TJ = 125C
8
4 0 0 25 50 75
VAUX = VAUX(on) - 0.2 V
100
125
150
Vin, LINE VOLTAGE (V)
Figure 5. Start-up Circuit Output Current versus Auxiliary Supply Voltage
IAUX, AUXILIARY SUPPLY CURRENT (mA) ISTART(off), START-UP CIRCUIT OFFSTATE LEAKAGE CURRENT (mA) 40 VAUX = 12 V 35 30 25 20 15 10 5 0 0 25 50 75 100 125 150 Vin, LINE VOLTAGE (V) TJ = 125C TJ = 25C TJ = -40C 4.0 3.5 3.0
Figure 6. Start-up Circuit Output Current versus Line Voltage
VAUX = 12 V VEA = 0 V
2.5 2.0 1.5 1.0 0.5 0 -50 -25 0 25 50 75 100 125 150 VUV/OV = 0 V
TJ, JUNCTION TEMPERATURE (C)
Figure 7. Start-up Circuit Off-State Leakage Current versus Line Voltage
Figure 8. Auxiliary Supply Current versus Junction Temperature
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NCP1560 Typical Characteristics
7 IAUX3, OPERATING AUXILIARY SUPPLY CURRENT (mA) VUV/OV, UV/OV VOLTAGE (V) 6 5 4 3 fOSC = 87 kHz 2 1 0 -50 -25 0 25 50 75 100 125 150 fOSC = 440 kHz VAUX = 12 V DC [ 50% fOSC = 300 kHz 4.0 3.5 OV THRESHOLD 3.0 2.5 2.0 1.5 UV THRESHOLD 1.0 0.5 0 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Operating Auxiliary Supply Current versus Junction Temperature
ILIM, CURRENT LIMIT THRESHOLDS (mV) 160 VUV/OV(H), UV/OV THRESHOLD VOLTAGE HYSTERESIS (mV) 150 140 130 120 110 100 90 -50 -25 0 UV HYSTERESIS OV HYSTERESIS 600 575 550 525 500
Figure 10. Line Under/Overvoltage Thresholds versus Junction Temperature
CYCLE SKIP
CYCLE BY CYCLE 475 450 425 400 -50 -25 0 25 50 75 100 125 150
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 11. Line Under/Over Voltage Thresholds Hysteresis versus Junction Temperature
fosc, OSCILLATOR FREQUENCY (kHz) 120 115 tILIM, CURRENT LIMIT PROPAGATION DELAY (ns) 110 105 100 95 90 85 80 75 70 -50 -25 0 25 50 75 100 125 150 VAUX = 12 V Measured from VOH to 0.5 VOH 450 400 350 300 250 200 150 100 50 0 -50
Figure 12. Current Limit Thresholds versus Junction Temperature
RT = 68 kW
RT = 101 kW
RT = 390 kW -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. Current Limit Propagation Delay versus Junction Temperature
Figure 14. Oscillator Frequency versus Junction Temperature
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NCP1560 Typical Characteristics
fosc, OSCILLATOR FREQUENCY (kHz) fosc, OSCILLATOR FREQUENCY (kHz) 315 310 RT = 101 kW 305 300 295 290 285 -50 600 500 400 300 200 100 0 50 100 150 200 250 300 350 400 RT, TIMING RESISTOR (kW) TJ = 25C DC [ 50%
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 15. Oscillator Frequency versus Junction Temperature
FEEDFORWARD INTERNAL RESISTANCE (kW) 19 18 17 16 15 14 13 12 11 10 9 -50 -25 0 25 50 75 100 125 90 80 70 60 50 40 30 20 10 0 0
Figure 16. Oscillator Frequency versus Timing Resistor
DCMAX, MAXIMUM DUTY CYCLE (%)
Vin = 36 V VEA = 3.0 V VDCMAX = 0 V
TJ = -40C
TJ = 125C
150
75
150
225
300
375
450
525
TJ, JUNCTION TEMPERATURE (C)
IFF, FEEDFORWARD CURRENT (mA)
Figure 17. Feedforward Internal Resistance versus Junction Temperature
100 Vin = 36 V RFF = 432 kW 90 RP = OPEN, RMDP = OPEN 80 ISS(C), SOFT START CHARGE CURRENT (mA) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 -50
Figure 18. Maximum Duty Cycle versus Feedforward Current
ISS(D), SOFT START DISCHARGE CURRENT (mA) 70 CHARGE 65 60 55 DISCHARGE 50 45 40 35 -25 0 25 50 75 100 30 125 150
DCMAX, MAXIMUM DUTY CYCLE (%)
70 RP = 0 W, RMDP = OPEN 60 50 -50
-25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 19. Maximum Duty Cycle versus Junction Temperature
Figure 20. Soft Start Charge/Discharge Currents versus Junction Temperature
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NCP1560 Typical Characteristics
RIN(VEA), VEA INPUT RESISTANCE (kW) VEA(L), PWM COMPARATOR LOWER INPUT THRESHOLD (V) 50 0.85
40
0.75
30
0.65
20
0.55
10 0 -50
0.45 0.35 -50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 21. VEA Input Resistance versus Junction Temperature
5.03 VREF, REFERENCE VOLTAGE (V) 350 tD, OUTPUTS OVERLAP DELAY (ns) 300 250 200 150 100 50 0 -50
Figure 22. PWM Comparator Lower Input Threshold versus Junction Temperature
5.01 IREF = 0 mA 4.99 IREF = 6 mA 4.97
RD = 1 MW, LEADING
RD = 60 kW, LEADING
4.95 4.93 -50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 23. Reference Voltage versus Junction Temperature
225 tD, OUTPUTS OVERLAP DELAY (ns) TJ = 25C 200 175 150 125 100 75 50 0 200 400 600 800 1000 RD, DELAY RESISTOR (kW) TRAILING LEADING RSNK/SRC OUTPUTS DRIVE RESISTANCE (W) 200
Figure 24. Outputs Overlap Delay versus Junction Temperature
160
Vin = 36 V VAUX = 12 V RMDP = 100 kW
120 RSRC (VEA = 0 V, VOUT = 10 V)
80
40 RSNK (VEA = 3 V, VOUT = 2 V) 0 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
Figure 25. Outputs Overlap Delay versus Delay Resistor
Figure 26. Outputs Drive Resistance Voltage versus Junction Temperature
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NCP1560 Typical Characteristics
80 ton, OUTPUTS RISE TIME (ns) TJ = 125C toff, OUTPUTS FALL TIME (ns) 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 200 CL, LOAD CAPACITANCE (pF) TJ = -40C Measured from 10% to 90% of VOH VAUX = 12 V TJ = 25C 35 Measured from 90% to 10% of VOH 30 VAUX = 12 V 25 20 15 10 5 0 0 25 50 75 100 125 150 175 200 CL, LOAD CAPACITANCE (pF) TJ = 25C TJ = 125C
TJ = -40C
Figure 27. Outputs Rise Time versus Load Capacitance
Figure 28. Outputs Fall Time versus Load Capacitance
DETAILED OPERATING DESCRIPTION The NCP1560 PWM controller contains all the features and flexibility needed for implementation of Voltage-Mode Control in high performance DC/DC converters. This device cost effectively reduces system part count with the inclusion of a high voltage start-up regulator. The NCP1560 provides two control outputs. Output 1 controls the main switch of a forward or flyback topology. Output 2 has an adjustable overlap delay, which can be used to control an active clamp/reset switch, a synchronous rectifier switch, or both. Other distinctive features include: two mode overcurrent protection, line under/over voltage lockout, fast line feedforward, soft start and a maximum duty cycle limit. The Functional Block Diagram is shown in Figure 2. The features included in the NCP1560 provide all the advantages of Current-Mode Control, fast line feedforward, and cycle by cycle current limit. It eliminates the disadvantages of low power jitter, slope compensation and noise susceptibility. High Voltage Start-up Regulator The NCP1560 contains an internal high voltage start-up regulator that eliminates the need for external start-up components. In addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. The start- up regulator consists of a constant current source that supplies current from the input line voltage (Vin) to the capacitor on the VAUX pin (CAUX). The start- up current is typically 13.8 mA. Once VAUX reaches 11 V, the start- up regulator turns OFF and the outputs are enabled. When VAUX reaches 7 V, the outputs are disabled and the start- up regulator turns ON. This "7- 11" mode of operation is known as Dynamic Self Supply (DSS). The VAUX pin can be biased externally above 7 V once the outputs are enabled to prevent the start-up regulator from turning ON. It is recommended to bias the VAUX pin using an auxiliary supply generated out of an auxiliary winding from the power transformer. An independent voltage supply can also be used. However, if VAUX is biased before the outputs are enabled or while a fault is present, the One Shot Pulse Generator (Figure 2) will not be enabled and the outputs will remain OFF. As the DSS sources current to the VAUX pin, a diode should be placed between CAUX and the auxiliary supply as shown in Figure 29. This will allow the NCP1560 to charge CAUX while preventing the start- up regulator from sourcing current into the auxiliary supply.
ISTART Vin 13.8 mA VAUX IAUX Disable CAUX To auxiliary supply
Isupply
Figure 29. Recommended VAUX Configuration
Power to the controller while operating in the self-bias or DSS mode is provided by CAUX. Therefore, CAUX must be sized such that a VAUX voltage greater than 7 V is maintained while the outputs are switching and the converter reaches regulation. Also, the VAUX discharge time (from 11 V to 7 V) must be greater that the soft start charge period to assure the converter turns ON. The start-up circuit is rated at a maximum voltage of 150 V. If the device operates in the DSS mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller.
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NCP1560
Line Under/Over Voltage Shutdown The NCP1560 incorporates a line under/over voltage shutdown (UV/OV) circuit. The under voltage (UV) threshold is 1.52 V and the over voltage threshold (OV) is 3.61 V, for a ratio of 1:2.4. The UV/OV circuit can be biased using an external resistor divider from the input line. The resistor divider must
VAUX(on) VAUX VAUX(off)
be sized to enable the controller once Vin is within the required operating range. If the UV or OV threshold is reached, the soft start capacitor is discharged, and the outputs are immediately disabled with no overlap delay as shown in Figure 30. Also, if an UV condition is detected, the 5.0 V Reference Supply is disabled.
0V VOV UV/OV Voltage VUV 0V
UV or OV Fault Propagation delay to outputs (tUV or tOV)
OUT2
0V
OUT1
0V
Figure 30. UV/OV Fault Timing Diagram
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NCP1560
Once the UV or OV condition is removed and VAUX reaches 11 V, the controller initiates a soft start cycle. Figure 31 shows the relationship between the UV/OV voltage, the outputs and the soft start voltage. The UV/OV pin can also be used to implement a remote enable/disable function. Biasing the UV/OV pin below its UV threshold disables the converter.
SOFT START VAUX(on) VAUX VAUX(off) 0V 2V 0V Soft Start Voltage 0V UV/OV Voltage
OUT2 0V
OUT1 0V
Figure 31. Soft Start Timing Diagram (Using Auxiliary Winding)
Feedforward Ramp Generator The NCP1560 incorporates line feedforward (FF) to compensate for changes in line voltage. A FF Ramp proportional to Vin is generated and compared to VEA. If the line voltage changes, the FF Ramp slope changes accordingly. The duty cycle will be adjusted immediately instead of waiting for the line voltage change to propagate around the system and be reflected back on VEA. A resistor between Vin and the FF pin (RFF) sets the feedforward current (IFF). The FF Ramp is generated by charging an internal 10 pF capacitor (CFF) with a constant current proportional to IFF. The FF Ramp is finished (capacitor is discharged) once the Oscillator Ramp reaches 2.0 V. Please refer to Figure 2 for a functional drawing of the Feedforward Ramp generator. IFF is usually a few hundred microamps, depending on the operating frequency and the required duty cycle. If the operating frequency and maximum duty cycle are known, IFF is calculated using the equation below:
IFF + CFF VDC(inv) 125 kW 6.7 kW ton(max)
Figure 18 shows the relationship between IFF and DCMAX. For example, if a system is designed to operate at 300 kHz, with a 60% maximum duty cycle at 36 V, the DCMAX pin can be grounded and IFF is calculated as follows:
1 T+1+ + 3.33 ms 300 kHz f ton(max) + DCMAX IFF + + T + 0.6 3.33 ms + 2.0 ms
CFF VDC(inv) 125 kW 6.7 kW ton(max) 10 pF 0.888 V 125 kW + 82.8 mA 6.7 kW 2.0 ms
As the minimum line voltage is 36 V, the required feedforward resistor is calculated using the equation below:
V RFF + in * 12.0 kW + 36 V * 12.0 kW [ 434 kW IFF 82.8 mA
where VDC(inv) is the voltage on the inverting input of the Max DC Comparator and ton(max) is the maximum ON time.
From the above calculations it can be observed that IFF is controlled predominantly by the value of RFF, as the resistance seen into the FF pin is only 12 kW. If a tight maximum duty cycle control over temperature is required, RFF should have a low thermal coefficient.
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NCP1560
Current Limit The NCP1560 has two over current protection modes, cycle by cycle and cycle skip. It allows the NCP1560 to handle momentary and hard shorts differently for the best tradeoff in performance and safety. The outputs are disabled typically 90 ns after a current limit fault is detected. The cycle by cycle mode terminates the conduction cycle (reducing the duty cycle) if the voltage on the CS pin exceeds 0.48 V. The cycle skip mode is enabled if the voltage on the CS pin reaches 0.57 V. Once a cycle skip fault is detected, the outputs are disabled, the soft start and cycle skip capacitors are discharged, and the cycle skip period (TCSKIP) commences.
NORMAL OPERATION VAUX(on) VAUX VAUX(off) 0V ILIM1 ILIM2
The cycle skip period is set by an external capacitor (CCSKIP). Once a cycle skip fault is detected, the cycle skip capacitor is discharged followed by a charge cycle. The charge current is 12.3 mA. The cycle skip period ends when the voltage on the cycle skip capacitor reaches 2.0 V. The cycle skip capacitor is calculated using the equation below:
CCSKIP [ TCSKIP 2V 12.3 mA
Using the above equation, a cycle skip period of 11.0 ms requires a cycle skip capacitor of 68 pF. The differences between the cycle by cycle and cycle skip modes are observed in Figure 32.
NORMAL OPERATION
RESET
SOFT START
OUT2
0V
OUT1
0V ILIM2 ILIM1 CS Voltage 0V TCSKIP Cycle Skip Voltage
0V
Figure 32. Over Current Faults Timing Diagram
Once the cycle skip period is complete and VAUX reaches 11 V, a soft start sequence commences. The possible minimum OFF time is set by CCSKIP. However, the actual OFF time is generally greater than the cycle skip period because it is the cycle skip period added to the time it takes VAUX to reach 11 V. Oscillator The NCP1560 oscillator frequency is set by a single external resistor connected between the RT pin and GND. The oscillator is designed to operate up to 500 kHz.
The voltage on the RT pin is laser trim adjusted during manufacturing to 1.3 V for an RT of 101 kW. A current set by RT generates an Oscillator Ramp by charging an internal 10 pF capacitor as shown in Figure 2. The period ends (capacitor is discharged) once the Oscillator Ramp reaches 2.0 V. If RT increases, the current and the Oscillator Ramp slope decrease, thus reducing the frequency. If RT decreases, the opposite effect is obtained. Figure 16 shows the relationship between RT and the oscillator frequency.
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NCP1560
Maximum Duty Cycle A dedicated internal comparator limits the maximum ON time of OUT1 by comparing the FF Ramp to VDC(inv). If the FF Ramp voltage exceeds VDC(inv), the output of the Max DC Comparator goes high. This will reset the Output Latch, thus turning OFF the outputs and limiting the duty cycle. Duty cycle is defined as:
t DC + on + ton T f
5.0 V Reference The NCP1560 includes a precision 5.0 V reference output. The reference output is biased directly from VAUX and it can supply up to 6 mA. Load regulation is 50 mV and line regulation is 100 mV within the specified operating range. It is recommended to bypass the reference output with a 0.1 mF ceramic capacitor. The reference output is disabled when an UV fault is present. PWM Comparator The output of an external error amplifier is compared to the FF Ramp by means of the PWM Comparator. The external error amplifier drives the VEA input. There is a 0.7 V offset between the VEA input and the PWM Comparator inverting input. The offset is provided by a series diode and resistor. If the voltage on the VEA input is below 0.7 V, the outputs are disabled. The PWM Comparator controls the duty cycle by turning OFF the outputs once the FF Ramp voltage exceeds the offset VEA voltage. The VEA range required to control the DC from 0% to DCMAX is given by the equation below:
VEA(L) t VEA t IFF DC ) VEA(L) 186.56 pf f
Therefore, the maximum ON time can be set to yield the desired DC if the operating frequency is known. The maximum ON time is set by adjusting the FF Ramp to reach VDC(inv) in a time equal to ton(max) as shown in Figure 33. The maximum ON time should be set for the minimum line voltage. As line voltage increases, the slope of the FF Ramp increases. This reduces the duty cycle below DCMAX, which is a desirable feature as the duty cycle is inversely proportional to line voltage.
Oscillator Ramp 2V
0V
T
where, VEA(L) is the PWM comparator lower input threshold.
VDC(inv)
FF Ramp 0V ton(max)
Figure 33. Maximum ON Time Limit Waveforms
An internal resistor divider from a 2.0 V reference is used to set VDC(inv). If the DCMAX pin is grounded, VDC(inv) is 0.88 V. If the pin is floating, VDC(inv) is 1.19 V. This is equivalent to 60% or 80% of a 1.5 V FF Ramp. VDC(inv) can be adjusted to other values by using an external resistor network on the DCMAX pin. For example, if the minimum line voltage is 36 V, RFF is 434 kW, operating frequency is 300 kHz and a maximum duty cycle of 70% is required, VDC(inv) is calculated as follows:
VDC(inv) + VDC(inv) + IFF 6.7 kW CFF ton(max) 125 kW
Soft Start Soft start (SS) allows the converter to gradually reach steady state operation, thus reducing start-up stress and surges on the system. The duty cycle is limited during a soft start sequence by comparing the Oscillator Ramp to the SS voltage (VSS) by means of the Soft Start Comparator. A 6.2 mA current source starts to charge the capacitor on the SS pin once faults are removed and VAUX reaches 11 V. The Soft Start Comparator controls the duty cycle while the SS voltage is below 2.0 V. Once VSS reaches 2.0 V, it exceeds the Oscillator Ramp voltage and the Soft Start Comparator does not limit the duty cycle. Figure 34 shows the relationship between the outputs duty cycle and the soft start voltage.
Oscillator Ramp VSS
88.2 mA 6.7 kW 2.33 ms +1.10 V 10 pF 125 kW
OUT2
This can be achieved by connecting a 45.3 kW resistor from the DCMAX pin to GND. The maximum duty cycle limit can be disabled connecting a 100 kW resistor between the DCMAX and VREF pins.
OUT1
Figure 34. Soft Start Timing Diagram
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NCP1560
If the soft start period is too long, VAUX may discharge to 7 V before the converter output is completely in regulation causing the outputs to be disabled. If the converter output is not completely discharged when the outputs are re-enabled, the converter will eventually reach regulation exhibiting a non-monotonic start-up behavior. But, if the converter output is completely discharged when the outputs are re-enabled, the cycle may repeat and the converter will not start. In the event of an UV, OV, or cycle skip fault, the soft start capacitor is discharged. Once the fault is removed, a soft start cycle commences. The soft start steady state voltage is approximately 4.1 V. Control Outputs The NCP1560 has two in-phase control outputs, OUT1 and OUT2, with adjustable overlap delay (tD). OUT2 precedes OUT1 during a low to high transition and OUT1 precedes OUT2 at any high to low transition. Figure 35 shows the relationship between OUT1 and OUT2.
tD (Leading) OUT1 tD (Trailing)
The control outputs are biased from VAUX. The outputs can supply up to 10 mA each and their high state voltage is usually 0.2 V below VAUX. Therefore, the auxiliary supply voltage should not exceed the maximum input voltage of the driver stage. If the control outputs need to drive a large capacitive load, a driver should be used between the NCP1560 and the load. ON Semiconductor's MC33152 is a good selection for an integrated driver. Figures 27 and 28 shows the relationship between the output's rise and fall times vs capacitive load. Time Delay The overlap delay between the outputs is set connecting a resistor (RD) between the tD and VREF pins. A minimum overlap delay of 80 ns is obtained when RD is 60 kW. If RD is not present, the delay is 200 ns. The output duty cycle can be adjusted from 0% to 85% selecting appropriate values of RFF and VDC(inv). It should be noted that the overlap delay may cause OUT2 to reach 100% duty cycle. Therefore, if OUT2 is used, the maximum duty cycle of OUT2 needs to be kept below 100%. The maximum overlap delay, tD(max), depends on the maximum duty cycle and frequency of operation. The maximum overlap delay is calculated using the equation below.
tD(max) v (1 * DC) 2
OUT2
Figure 35. Control Outputs Timing Diagram
Generally, OUT1 controls the main switching element. Output 2, once inverted, can control a synchronous rectifier. The overlap delay prevents simultaneous conduction. Output 2 can also be used to control an active clamp reset. Once VAUX reaches 11 V, the internal start-up circuit is disabled and the One Shot Pulse Generator is enabled. If no faults are present, the outputs turn ON. Otherwise, the outputs remain OFF until the fault is removed and VAUX reaches 11 V again.
For example, if the converter operates at a frequency of 300 kHz with a maximum duty cycle of 80%, the maximum allowed overlap delay is 333 ns. However, this is a theoretical limit and variations over the complete operating range should be considered when selecting the overlap delay. Additional Information A 100 W DC-DC converter for telecom systems was designed and implemented using the NCP1560. The converter design is discussed in Application Note AND8105/D.
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PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -TSEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
The product described herein (NCP1560) may be covered by one or more U.S. patents. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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